FIG. 1 shows a prior art six transistor static read/write memory cell 710 such as is typically used in high-density static random access memories (SRAMs). A static memory cell is characterized by operation in one of two mutually-exclusive and self-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a "high" voltage to indicate a "set" operating state. The memory cell output produces a "low" voltage to indicate a "reset" operating state. A low or reset output voltage usually represents a binary value of zero, while a high or set output voltage represents a binary value of one.
Static memory cell 710 generally comprises first and second inverters 712 and 714 which are cross-coupled to form a bistable flip-flop. Inverters 712 and 714 are formed by n-channel driver transistors 716 and 717, and p-channel load transistors 718 and 719. Driver transistors 716 and 717 are typically n-channel metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate. P-channel transistors 718 and 719 are typically thin film transistors formed above the driver transistors.
The source regions of driver transistors 716 and 717 are tied to a low reference or circuit supply voltage, labelled V.sub.SS and typically referred to as "ground." Load transistors 718 and 719 are connected in series between a high reference or circuit supply voltage, labelled V.sub.CC, and the drains of the corresponding driver transistors 716 and 717. The gates of load transistors 718 and 719 are connected to the gates of the corresponding driver transistors 716 and 717.
Inverter 712 has an inverter output 720 formed by the drain of driver transistor 716. Similarly, inverter 714 has an inverter output 722 formed by the drain of driver transistor 717. Inverter 712 has an inverter input 724 formed by the gate of driver transistor 716. Inverter 714 has an inverter input 726 formed by the gate of driver transistor 717.
The inputs and outputs of inverters 712 and 714 are cross-coupled to form a flip-flop having a pair of complementary two-state outputs. Specifically, inverter output 720 is cross-coupled to inverter input 726, and inverter output 722 is cross-coupled to inverter input 724. In this configuration, inverter outputs 720 and 722 form the complementary twostate outputs of the flip-flop.
A memory flip-flop such as that described typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 730 and 732, are used to selectively address and access individual memory elements within the array. Access transistor 730 has one active terminal connected to cross-coupled inverter output 720. Access transistor 732 has one active terminal connected to cross-coupled inverter output 722. A plurality of complementary column line pairs, such as the single pair of complementary column lines 734 and 736 shown, are connected to the remaining active terminals of access transistors 730 and 732, respectively. A row line 738 is connected to the gates of access transistors 730 and 732.
Reading static memory cell 710 involves activating row line 738 to connect inverter outputs 720 and 722 to column lines 734 and 736. Writing to static memory cell 710 involves first placing selected complementary logic voltages on column lines 734 and 736, and then activating row line 738 to connect those logic voltages to inverter outputs 720 and 722. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
FIG. 2 shows an alternative four transistor, dual wordline, prior art static read/write memory cell 750 such as is typically used in high-density static random access memories. Static memory cell 750 comprises n-channel pull-down (driver) transistors 780 and 782 having drains respectively connected to pull-up load elements or resistors 784 and 786. Transistors 780 and 782 are typically metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate.
The source regions of transistors 780 and 782 are tied to a low reference or circuit supply voltage, labelled V.sub.SS and typically referred to as "ground." Resistors 784 and 786 are respectively connected in series between a high reference or circuit supply voltage, labelled V.sub.CC, and the drains of the corresponding transistors 780 and 782. The drain of transistor 782 is connected to the gate of transistor 780 by line 776, and the drain of transistor 780 is connected to the gate of transistor 782 by line 774 to form a flip-flop having a pair of complementary two-state outputs.
A memory flip-flop, such as that described above in connection with FIG. 2, typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 790 and 792, are used to selectively address and access individual memory elements within the array. Access transistor 790 has one active terminal connected to the drain of transistor 780. Access transistor 792 has one active terminal connected to the drain of transistor 782. A plurality of complementary column line pairs, such as the single pair of complementary column lines 752 and 754 shown, are connected to the remaining active terminals of access transistors 790 and 792, respectively. A row line 756 is connected to the gates of access transistors 790 and 792.
Reading static memory cell 750 involves activating row line 756 to connect outputs 768 and 772 to column lines 752 and 754. Writing to static memory cell 750 involves first placing selected complementary logic voltages on column lines 752 and 754, and then activating row line 756 to connect those logic voltages to outputs 768 and 772. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
A static memory cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The two possible output voltages produced by a static memory cell correspond generally to upper and lower circuit supply voltages. Intermediate output voltages, between the upper and lower circuit supply voltages, generally do not occur except for during brief periods of memory cell power-up and during transitions from one operating state to the other operating state.
The operation of a static memory cell is in contrast to other types of memory cells such as dynamic cells which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than very short time periods.
A dynamic memory cell has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the four or more transistors typically required in a static memory cell. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along generally different paths than has the design of dynamic memories.
FIG. 3 illustrates a typical top view of a prior art layout of portions of the FIG. 2 SRAM schematic pertinent to this disclosure. Such an SRAM cell employs two V.sub.CC lines which are labeled respectively as Vcc(A) and Vcc(B). Lines 790a and 792a constitute the gate or wordlines of access devices 790 and 792, respectively. The two shaded areas 784 and 786 comprise the described pull-up resistors which are substantially horizontally formed as shown within the SRAM cell. Such horizontal positioning consumes considerable area within an individual SRAM cell, thus countering a desired goal of maximizing circuit density. Other examples of such similarly situated resistors can be found in U.S. Pat. No. 4,178,674 to Liu et al. and U.S. Pat. No. 4,828,629 to Akeda et al. Vertically oriented pull-up resistor constructions in SRAM cells have been proposed, such as is disclosed s in our U.S. Pat. No. 5,177,030.
This invention principally arose from concerns associated with fabrication of improved SRAMs employing vertically elongated pull-up resistors. However the artisan will appreciate applicability of the invention to resistor constructions in general, with the invention only being limited by the accompanying claims appropriately interpreted with the Doctrine Of Equivalents.